1. Field
A liquid crystal display device using a horizontal electric field and a fabricating method thereof are provided.
2. Related Art
Generally, a liquid crystal display device controls light transmittance of a liquid crystal having a dielectric anisotropy using an electric field to display a picture. Such liquid crystal display devices are largely classified into vertical electric field applying types and horizontal electric field types depending upon the direction of the electric field driving the liquid crystal.
The liquid crystal display device of vertical electric field types drive a liquid crystal with a vertical electric field that is formed between a pixel electrode and a common electrode, which are arranged in opposition to each other on the upper and lower substrate. Liquid crystal display devices of the vertical electric field type have a large aperture ratio while having a a narrow viewing angle about 90°.
The liquid crystal display device of horizontal electric field types drive a liquid crystal with a horizontal electric field that is between the pixel electrode and the common electrode, which are arranged in parallel to each other on the lower substrate. An example of a liquid crystal display device of horizontal electric field type is an in plane switching (IPS) mode. Liquid crystal display devices of horizontal electric field type have a wide viewing angle of approximately about 160°. Hereinafter, the liquid crystal display device of horizontal electric field type will be described in detail.
A liquid crystal display device of horizontal electric field type includes a thin film transistor substrate (lower substrate) and a color filter array substrates (upper substrate) that are opposed to each other and united. A spacer constantly keeps a cell gap between the two substrates. A liquid crystal is disposed in the cell gap.
FIG. 1 is a plan view showing a portion of a related art thin film transistor substrate of a horizontal electric field type, and FIG. 2 is a section view of the thin film transistor substrate taken along the I-I′ and II-II′ lines in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 45. The gate line 2 and the data line 4 are disposed in such a manner that intersects each other and have a gate insulating film 46 therebetween. A thin film transistor 6 is formed at each intersection. A pixel electrode 14 and a common electrode 18 provide a horizontal electric field at a pixel area that is defined by an intersection structure. A common line 16 is connected to the common electrode 18. The thin film transistor substrate further includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 14 and a common electrode line 16. A gate pad 24 is connected to the gate line 2. A data pad 30 is connected to the data line 4 and a common pad 36 is connected to the common line 16.
The gate line 2 that supplies a gate signal and the data line 4 that supplies a data signal are provided in an intersection structure to define a pixel area.
The common line 16 supplies a reference voltage that drives the liquid crystal is formed in parallel to the gate line 2 with the pixel area disposed therebetween.
The thin film transistor 6 allows a pixel signal applied to the data line 4 to be charged into the pixel electrode 14 and be kept in response to a scanning signal applied to the gate line 2. The thin film transistor 6 includes a gate electrode 8 that is connected to the gate line 2. A source electrode 10 is connected to the data line 4. A drain electrode 12 is connected to the pixel electrode 14. An active layer 48 overlaps with the gate electrode 8 with a gate insulating film 46 disposed therebetween to define a channel between the source electrode 10 and the drain electrode 12. An ohmic contact layer 50 makes an ohmic contact with the source electrode 10, the drain electrode 12 and an active layer 48.
The active layer 48 and the ohmic contact layer 50 are formed in such a manner to overlap with the data line 4, a lower data pad electrode 32 and an upper storage electrode 22.
The pixel electrode 14 is connected, via a first contact hole 13 passing through a protective film 52, to the drain electrode 12 of the thin film transistor 6 and formed at the pixel area. The pixel electrode 14 includes a first horizontal portion 14A connected to the drain electrode 12 and formed in parallel to the adjacent gate line 2. A second horizontal portion 14B is formed in such a manner that overlaps with the common line 16 and a finger portion 14C formed in parallel between the first and second horizontal portions 14A and 14B.
The common electrode 18 is connected to the common line 16 and is formed at the pixel area 5. The common electrode 18 is formed in parallel to the finger portion 14C of the pixel electrode 14 at the pixel area 5.
A horizontal electric field is formed between the pixel electrode 14 supplied with a pixel signal, via the thin film transistor 6 and the common electrode 18 supplied with a reference voltage (Hereinafter, a common electrode), via the common line 16. More specifically, a horizontal electric field is formed between the finger portion 14C of the pixel electrode 14 and the common electrode 18. Liquid crystal molecules that are arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate by such a horizontal electric field are rotated due to a dielectric anisotropy. Transmittance of a light that transmits the pixel area is differentiated depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.
The storage capacitor 20 is comprised of the common line 16, and the upper storage electrode 22 that overlaps with the common line 16 with has the gate insulating film 46, the active layer 48 and the ohmic contact layer 50 therebetween and connected, via a second contact hole 21 provided on a protective film 50, to the pixel electrode 14. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 14 to be maintained in a stable state until the next signal is charged.
The gate line 2 is connected, via the gate pad 24, to the gate driver (not shown). The gate pad 24 is comprised of a lower gate pad electrode 26 extended from the gate line 2 and an upper gate pad electrode 28 connected, via a third contact hole 27 passing through the gate insulating film 46 and a protective film 52, to the lower gate pad electrode 26.
The data line 4 is connected, via the data pad 30, to the data driver (not shown). The data pad 30 is comprised of a lower data pad electrode 32 extended from the data line 4 and an upper data pad electrode 34 connected, via a fourth contact hole 33 passing through the protective film 52, to the lower data pad electrode 32.
The common line 16 is supplied, via a common pad 36, with a common voltage from a common voltage source (not shown). The common pad 36 is comprised of a lower common pad electrode 38 that extends from the common line 16 and an upper common pad electrode 40 connected, via a five contact hole 39 passing through the gate insulating film 46 and the protective film 52, to the lower common pad electrode 38.
The common electrode 18 provided at the pixel area is formed from an opaque gate metal and has a low aperture ratio.
There is a limit to the overlapping area between the common electrode 16 formed from an opaque metal and the upper storage electrode 22 by an aperture ratio. Accordingly, the capacitance of the storage capacitor 20 is limited.
A related art thin film transistor substrate of a liquid crystal display device of a horizontal electric field type is formed by a plurality of mask processes. One mask process includes a lot of sub-processes such as deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, and it has a complicated fabricating process.